The present invention relates to a system processing an inter-processor communication instruction from a service processor in a multiprocessor system adopting a split bus control method.
In a multiprocessor system, individual processors must work cooperatively. For this purpose, each processor may request a status message from another processor, or request some processing thereto. A so-called inter-processor communication instruction is used to implement such a function.
The system of this type includes a service processor which performs maintenance servicing of other processors, as well as serving as a console or the like.
In the system of this type, a single processor can control all the other processors by sending a processing request to the other processors simultaneously, using a common inter-processor communication instruction (to be called a 1:n inter-processor communication instruction hereinafter). In this case, a single processor outputs the common inter-processor communication instruction onto a system bus. The other processors connected to the system bus receive this instruction at substantially the same time and perform the requested processing. The operation rates of the processors are thus substantially the same.
The 1:n inter-processor communication requires n interfaces for processing responses from n processors. However, the interfaces are provided to regular processors in the system, but not provided to the service processor. Thus, it is impossible to send a simultaneous processing request from the service processor to the other processors. Therefore, the service processor must sequentially send inherent inter-processor communication instructions (to be called 1:1 inter-processor communication instructions hereinafter) corresponding to the respective processors to sequentially control them. In this case, processing timings of the respective processors differ. In addition, since the operation rate of the service processor is lower than that of the regular processors, the lag in operation timings is increased.
On the other hand, providing an interface in the service processor results in bulky hardware, complicated control, and increased cost.
In a multiprocessor system adopting a split bus control method, a system bus is released every one bus cycle. During processing requested by the inter-processor communication instruction, data are shuttled between the corresponding processors (that is, several requests for obtaining the system bus are established). Therefore, before the processing associated with a given inter-processor communication instruction is completed, a processor may receive another inter-processor communication instruction. Such a problem may not frequently occur. However, each processor requires complicated hardware and firmware to avoid the above contention.